CS61CPU: a 32-bit RISC-V processor, built from gates

CS 61C · Logisim Evolution · Summer 2025

I built a 32-bit RISC-V processor from gates, then re-architected the single-cycle design into a two-stage pipeline.

36 instructions: 8 I-type, 12 R-type incl. mul/mulh/mulhu, 6 branch, 6 load/store, 4 jump and upper-immediate.
32-register file, x0 hardwired to zero, 2 read ports; 5 immediate encoding formats; byte/halfword lane logic.
9 control signals decoded from the instruction word, widest the 4-bit ALUSel.
Single-cycle re-architected to a 2-stage pipeline. Decode and writeback share a stage, so there are no data hazards, and every hazard is control, flushed with the nop 0x00000013.
12 integration tests compile real RISC-V onto the circuit and diff 8 registers against Venus. Memory is not compared, so a store bug passes all of them.
8-week summer session: 1 week between the single-cycle and pipelined deadlines, against ~3 in the regular term.

Logisim Evolution · RISC-V · pipelining · digital design